Distributed power management is a key technology enabling portable battery powered devices. Power management enables increased run time, reduction in battery size, lower heat dissipation, and lower device weight. Prior power management techniques centered on a central power management circuit. The power management circuit or power control module is located on a circuit board or in the system that gates power to various circuits in the system. The single power management controller ensured the various circuits would power back up in phase with the primary controller or system clock.
As integrated circuits have grown in complexity and are increasingly used for battery powered devices where available power is limited, distributed power management is increasingly used to extend battery life and reduce power consumption. In co-owned U.S. Pat. No. 7,840,239, entitled “DISTRIBUTED POWER MANAGEMENT”, issued Nov. 23, 2010 to inventors Indiani et. al., which is hereby incorporated by reference in its entirety herein, a power controller is disclosed that digitally sends a power down message to various sub-circuits.
With continuingly increasing device integration and as the number of devices within ICs increases, in-circuit power down techniques have developed. In these prior known approaches, various circuit sub-systems are identified and grouped into various power domains within the integrated circuit. The different power domains can be powered down when the sub-systems that are within the power domains are not in use. In a known approach, to enact the power down sequence, a finite state machine (FSM) controls a power down sequence for the various power managed domains. The FSM is placed in an always on domain (AOD) where a clock supplying the FSM is maintained so that the power down and wake-up will occur synchronously with the system clock. Other than receiving the clock pulses, the FSM is only active when a power down request is received or a wake-up is needed. In an ideal situation, only the FSM circuitry is included in the AOD. The overall power consumption of the integrated circuit device is reduced because during shutdown or sleep modes only the FSM is active. In practical integrated circuits, various functions that cannot be powered down, such as interrupt handlers, input/output controllers, and activity timers are included in the AOD along with the power down FSM.
At least two prior approaches have been used to further manage power consumption within the AOD. For a very low power approach, a very slow clock can be used within the AOD that is a multiple of a main clock. Because the power consumption in a conventional logic integrated circuit scales in proportion to clock frequency, the use of the slow running clock will lower power consumption. However, in the slow clock approach the integrated circuit or system including the FSM also has a slow wake-up time, and a slow response after a wake-up event. Another known approach is to run a faster clock that uses more power within the AOD, but that will result in an improved wake-up time. The higher power consumption can be reduced somewhat by gating the clock (thereby emulating a slower clock) during power down times; however, even with the use of the gated clock there will still be leakage power loss as the clock generating circuitry is still powered.